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UG380 (v2.7) October 29, 2014
Bitstream Encryption
Bitstream Encryption
The Spartan-6 6SLX75/T, 6SLX100/T, and 6SLX150/T devices have on-chip AES
decryption logic to provide a high degree of design security. Without knowledge of the
encryption key, potential pirates cannot analyze an externally intercepted bitstream to
understand or clone the design. Encrypted Spartan-6 FPGA designs cannot be copied or
reverse-engineered. Encryption is permitted in configuration modes of x1 and x8 data
widths (including JTAG). Encryption cannot be used in conjunction with bitstream
compression.
The Spartan-6 FPGA AES system consists of software-based bitstream encryption and
on-chip bitstream decryption with dedicated memory for storing the encryption key.
Using the ISE software, the user generates the encryption key and the encrypted bitstream.
Spartan-6 devices store the encryption key internally in either dedicated RAM, backed up
by a small externally connected battery, or the eFUSE. The encryption key can only be
programmed onto the device through the JTAG interface; once programmed and secured
with the Key Security bits, it is not possible to read the encryption key out of the device
through JTAG or any other means.
During configuration, the Spartan-6 device performs the reverse operation, decrypting the
incoming bitstream. The Spartan-6 FPGA AES encryption logic uses a 256-bit encryption
key.
The on-chip AES decryption logic cannot be used for any purpose other than bitstream
decryption; i.e., the AES decryption logic is not available to the user design and cannot be
used to decrypt any data other than the configuration bitstream.
Advanced Encryption Standard Overview
The Spartan-6 FPGA encryption system uses the AES encryption algorithm. AES is an
official standard supported by the National Institute of Standards and Technology (NIST)
and the U.S. Department of Commerce
(http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf)
.
The Spartan-6 FPGA AES encryption system uses a 256-bit encryption key (the alternate
key lengths of 128 and 192 bits described by NIST are not implemented) to encrypt or
decrypt blocks of 128 bits of data at a time. According to NIST, there are 1.1 x 10
77
possible
key combinations for a 256-bit key.
Symmetric encryption algorithms such as AES use the same key for encryption and
decryption. The security of the data is therefore dependent on the secrecy of the key.
Creating an Encrypted Bitstream
BitGen, provided with the ISE software, can generate encrypted as well as non-encrypted
bitstreams. For AES bitstream encryption, the user specifies a 256-bit key as an input to
BitGen. BitGen in turn generates an encrypted bitstream file (BIT) and an encryption key
file (NKY).
For specific BitGen commands and syntax, refer to UG628
, Command Line Tools User Guide.
- Spartan-6 FPGA 1
- Configuration 1
- Revision History 3
- Table of Contents 7
- Chapter 4: User Primitives 8
- Chapter 8: Readback CRC 10
- About This Guide 13
- Additional Resources 14
- Configuration Overview 15
- Design Considerations 16
- Slave Modes 17
- UG380_c1_02_051109 18
- Serial SelectMAP 18
- MultiBoot /Safe Update 20
- Required I/O Voltages 20
- Nonvolatile Data Storage 20
- FPGA Density Migration 21
- Production Lifetime 21
- Configuration Factors 22
- Chapter 2 23
- Master Serial 26
- Slave Serial Configuration 27
- Spartan-6 28
- Microprocessor 28
- Platform Flash 32
- SelectMAP Data Loading 35
- SelectMAP Data Ordering 39
- SPI Configuration Interface 40
- SPI Flash 42
- W25Q SPI 43
- UG380_c2_14_011310 44
- Master SPI Timing Waveform 45
- Power-On Sequence Precautions 46
- SPI Serial Daisy-Chain 47
- Chapter 3 59
- Data Valid 60
- User Primitives 65
- ICAP_SPARTAN6 66
- STARTUP_SPARTAN6 67
- SUSPEND_SYNC 68
- POST_CRC_INTERNAL 69
- Chapter 4: User Primitives 70
- Configuration Details 71
- Pin Name Type 72
- Description 72
- Bitstream Overview 75
- Generating PROM Files 77
- UG380_c5_01_042909 78
- Parallel Bus Bit Order 79
- Configuration Sequence 80
- Setup (Steps 1-3) 81
- UG380_c5_04_050812 82
- Sample Mode Pins (Step 3) 83
- UG380_c5_05_042909 83
- UG380_c5_06_042909 83
- Synchronization (Step 4) 84
- Check Device ID (Step 5) 84
- UG380_c5_07_042909 84
- UG380_c5_08_042909 84
- Startup (Step 8) 86
- Phase Event 87
- Signal Name Type Access 88
- Bitstream Encryption 89
- Loading the Encryption Key 90
- Loading Encrypted Bitstreams 90
- Configuration Memory Frames 95
- Type 1 Packet 96
- Type 2 Packet 96
- Configuration Registers 97
- CRC Register 98
- CBC_REG Register 100
- IDCODE Register 100
- CSBO Register 100
- Command Register (CMD) 100
- Control Register 0 (CTL) 101
- Status Register (STAT) 102
- Configuration Packets 103
- Suspend Register (PWRDN_REG) 104
- Frame Length Register 104
- Multi-Frame Write Register 104
- HC_OPT_REG Register 105
- MODE Register 106
- CCLK_FREQ Register 107
- PU_GWE Register 107
- PU_GTS Register 107
- SEU_OPT Register 108
- DNA_PORT 109
- UG380_c5_14_052009 110
- Read = 0 110
- X = Don’t care 110
- ↑ = Rising clock edge 110
- UG380_c5_15_121112 111
- UG380_c5_16_021010 111
- UG380_c5_17_052009 112
- UG380 (v2.7) October 29, 2014 113
- Readback and Configuration 115
- Verification 115
- Readback Command Sequences 116
- AA 99 55 66 28 00 E0 0 0 117
- Verifying Readback Data 127
- UG380_c6_04_042909 128
- MSK and BIT Files 129
- Reconfiguration and MultiBoot 131
- Fallback MultiBoot 132
- IPROG Reconfiguration 134
- Watchdog Timer 135
- Readback CRC 137
- CRC Masking 138
- Chapter 8: Readback CRC 140
- Distributed RAM 141
- Post_CRC Constraints 142
- POST_CRC 143
- POST_CRC_INIT_FLAG 143
- POST_CRC_SOURCE 143
- POST_CRC_ACTION 144
- POST_CRC_FREQ 144
- Chapter 9 145
- Mixed Serial Daisy-Chains 146
- Startup Sequencing (GTS) 147
- Active DONE Driver 147
- Connect All DONE Pins 147
- DONE Pin Rise Time 147
- Bitstream Formatting 147
- Parallel Daisy-Chain 151
- Ganged SelectMAP 152
- UG380_c9_06_021710 153
- ABORT Status Word 154
- SelectMAP Reconfiguration 155
- Advanced JTAG Configurations 157
- JTAG Configuration/Readback 158
- Boundary-Scan Register 161
- Instruction Register 162
- UG380_c10_03_102014 162
- BYPASS Register 164
- JTAG Configuration Register 164
- USERCODE Register 164
- Load CFG_IN 166
- Instruction 166
- Single Device Configuration 167
- Multiple Device Configuration 168
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