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14 www.xilinx.com Spartan-6 FPGA Configuration User Guide

UG380 (v2.7) October 29, 2014

Preface: About This Guide

•Spartan-6 FPGA Clocking Resources User Guide

This guide describes the clocking resources available in all Spartan-6 devices,

including the DCMs and the PLLs.

• Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan-6 device block RAM capabilities.

• Spartan-6 FPGA Configurable Logic Blocks User Guide

This guide describes the capabilities of the configurable logic blocks (CLBs) available

in all Spartan-6 devices.

• Spartan-6 FPGA Memory Controller User Guide

This guide describes the Spartan-6 FPGA memory controller block, a dedicated,

embedded multi-port memory controller that greatly simplifies interfacing Spartan-6

FPGAs to the most popular memory standards.

• Spartan-6 FPGA GTP Transceivers User Guide

This guide describes the GTP transceivers available in Spartan-6 LXT FPGAs.

• Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and

provides configuration examples.

• Spartan-6 FPGA PCB and Pin Planning Design Guide

This guide provides information on PCB design for Spartan-6 devices, with a focus on

strategies for making design decisions at the PCB and interface level.

• Spartan-6 FPGA Power Management User Guide

This guide provides information on the various hardware methods of power

management in Spartan-6 devices, primarily focusing on the suspend mode.

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm

To search the Answer Database of silicon, software, and IP questions and answers, or to

create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support

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Autostart PD-2.7 Guide de l'utilisateur Page 14