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Spartan-6 FPGA Configuration User Guide www.xilinx.com 67

UG380 (v2.7) October 29, 2014

STARTUP_SPARTAN6

The STARTUP_SPARTAN6 primitive provides a fabric interface to allow users to control

some of global signals after configuration.

DNA_PORT

The DNA_PORT provides access to a dedicated shift register, which can be loaded with the

Device DNA data bits (unique ID) for a given Spartan®-6 device. In addition to shifting

out the DNA data bits, this component allows for the inclusion of supplemental data bits

for additional user data or allow for the DNA data to rollover (repeat DNA data after

initial data has been shifted out). This component is primarily used in conjunction with

other circuitry to build anti-cloning protection for the FPGA bitstream from possible theft.

The DNA_PORT component must be instantiated to be used in a design. The instantiation

template is found within the ISE® software. Project Navigator HDL templates. The

instance declaration must be placed within the code. All inputs and outputs must be

connected to the design to ensure proper operation.

To access the Device DNA data, the shift register must first be loaded by setting the

active-High READ signal for one clock cycle. After the shift register is loaded, the data can

be synchronously shifted out by enabling the active-High SHIFT input and capturing the

data from the DOUT output port. If desired, additional data can be appended to the end of

the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data

Table 4-3: STARTUP_SPARTAN6 Port Description

Signal Name Type Function

EOS Output Active-High. Absolute end of startup.

CLK Input User startup clock.

GSR Input Active-High global set/reset signal. When this

input is asserted, all flip-flops are restored to their

initial value in the bitstream.

KEYCLEARB Input Clear the battery-backed RAM key when it is set.

This signal needs to stay Low for 200 ns (four clock

cycles) to enable KEYCLEAR function.

GTS Input Active-High global 3-state signal. When this input is

asserted, all user I/Os are 3-stated.

CFGMCLK Output Configuration internal oscillator clock output of

approximately 50 MHz that can be used as a generic

clock source instead of a ring oscillator in the FPGA

logic. If this port is not connected in the design, the

oscillator is disabled.

CFGCLK Output Configuration logic main clock output. This signal

outputs the clock associated with the current

configuration mode. If the FPGA is in a Slave

configuration mode, the clock source is CCLK. If the

FPGA is in a Master configuration mode, the clock

source is the internal oscillator frequency (as

defined by the BitGen option -g ConfigRate).

Use the BitGen Persist option to maintain this

signal after configuration.

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