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Spartan-6 FPGA Configuration User Guide www.xilinx.com 137

UG380 (v2.7) October 29, 2014

Chapter 8

Readback CRC

Spartan®-6 devices include a feature to perform continuous readback of configuration

data in the background of a user design. This feature is aimed at simplifying detection of

single event upsets (SEUs) that cause a configuration memory bit to flip. Detected failures

appear either on a device pin (INIT_B) and/or on an internally accessible component,

POST_CRC_INTERNAL. The clock source of the readback can be external or internally

generated.

Caution!

Continuous readback of configuration data using the built-in post-configuration CRC

checking (POST_CRC) or configuration frame read operations using ICAP can increase jitter on

SelectIO or GTP I/O. Increased jitter lowers the link margin and can cause bit errors. This issue

is limited to Spartan-6 devices. The Soft Error Mitigation IP core

includes a workaround for this

issue.

The expected “golden” CRC value is calculated by the software and written into the FPGA

for later comparison. The subsequent scans of Readback CRC value are compared against

the golden value. When a CRC mismatch is found, the CRCERROR pin of the

POST_CRC_INTERNAL primitive is driven High, the INIT_B pin is driven Low, and the

DONE pin remains High. The CONFIG user primitive attribute POST_CRC_INIT_FLAG

can be optionally set to DISABLE to disable INIT_B as a Readback CRC flag. The error flag

remains High until cleared.

Readback CRC is halted and the error flag cleared when:

• SYNC or DESYNC word is detected.

• JTAG TAP controller is reset.

• Abort is triggered through Slave SelectMAP or ICAP access.

• IPROG (internal program) command is received.

• Suspend mode is enabled.

• The device is in shutdown mode, such as readback shutdown, JSHUTDOWN, or

ISC_ENABLE.

The Readback CRC automatically stops without affecting the user configuration access,

and the error flag is cleared. When the user exits the condition that halted the readback, the

golden value CRC is recalculated and automatically resumes if POST_CRC is set to

ENABLE.

Readback CRC logic runs under these conditions:

• The FPGA has started up successfully, as indicated by the DONE pin going High.

• Any configuration operation must finish with a DESYNC command to release the

configuration logic. If a DESYNC command is not issued, the readback CRC logic

cannot access the configuration logic and cannot run.

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Autostart PD-2.7 Guide de l'utilisateur Page 137