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164 www.xilinx.com Spartan-6 FPGA Configuration User Guide

UG380 (v2.7) October 29, 2014

Chapter 10: Advanced JTAG Configurations

Table 10-3 shows the instruction capture values loaded into the IR as part of an instruction

scan sequence.

BYPASS Register

The other standard data register is the single flip-flop BYPASS register. It passes data

serially from the TDI pin to the TDO pin during a bypass instruction. This register is

initialized to zero when the TAP controller is in the CAPTURE-DR state.

Identification (IDCODE) Register

Spartan-6 devices have a 32-bit identification register called the IDCODE register. The

IDCODE is based on IEEE Std 1149.1 and is a fixed, vendor-assigned value that is used to

identify electrically the manufacturer and the type of device that is being addressed. This

boundary-scan, and it can be shifted out for examination by using the IDCODE

instruction.

The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex

digits appear as 0x093. IDCODEs assigned to Spartan-6 FPGAs are shown in Table 5-13.

JTAG Configuration Register

The JTAG Configuration register is a 16-bit register. This register allows access to the

configuration bus and readback operations.

USERCODE Register

The USERCODE instruction is supported in the Spartan-6 family. This register allows a

user to specify a design-specific identification code. The USERCODE can be programmed

into the device and can be read back for verification later. The USERCODE is embedded

into the bitstream during bitstream generation (BitGen -g UserID option) and is valid

only after configuration. If the device is blank or the USERCODE was not programmed,

the USERCODE register contains 0xFFFFFFFF.

USER1, USER2, USER3, and USER4 Registers

The USER1, USER2, USER3, and USER4 registers are only available after configuration.

These four registers must be defined by the user within the design. These registers can be

accessed after they are defined by the TAP pins.

The BSCAN_Spartan6 library macro is required when creating these registers. This symbol

is only required for driving internal scan chains (USER1, USER2, USER3, and USER4).

A common input pin (TDI) and shared output pins represent the state of the TAP controller

(RESET, SHIFT, and UPDATE). Spartan-6 FPGA TAP pins are dedicated and do not require

the BSCAN_Spartan6 macro for normal boundary-scan instructions or operations. For

HDL, the BSCAN_Spartan6 macro must be instantiated in the design.

Table 10-3: Instruction Capture Values

TDI → IR[5] IR[4] IR[3] IR[2] IR[1:0] → TDO

DONE INIT(1) ISC_ENABLED ISC_DONE 0 1

1 2 ... 159 160 161 162 163 164 165 166 167 168 169 170

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