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110 www.xilinx.com Spartan-6 FPGA Configuration User Guide

UG380 (v2.7) October 29, 2014

Chapter 5: Configuration Details

Identifier Value

As shown in Figure 5-14, the device DNA value is 57 bits long. The two most-significant

bits are always 1 and 0. The remaining 55 bits are unique to a specific Spartan-6 FPGA.

Operation

Figure 5-14 shows the general functionality of the DNA_PORT design primitive. An FPGA

application must first instantiate the DNA_PORT primitive, shown in Figure 5-13, within a

design.

To read the device DNA, the FPGA application must first transfer the identifier value into

the DNA_PORT output shift register. The READ input must be asserted during a rising

edge of CLK, as shown in Table 5-51. This action parallel loads the output shift register

with all 57 bits of the identifier. Because bit 56 of the identifier is always 1, the DOUT

output is also 1. The READ operation overrides a SHIFT operation.

To continue reading the identifier values, SHIFT must be asserted, followed by a rising

edge of CLK, as shown in Table 5-51. This action causes the output shift register to shift its

contents toward the DOUT output. The value on the DIN input is shifted into the shift

A Low-to-High transition on SHIFT should be avoided when CLK is High because this

causes a spurious initial clock edge. Ideally, SHIFT should only be asserted when CLK is

Low or on a falling edge of CLK.

If both READ and SHIFT are Low, the output shift register holds its value and DOUT

remains unchanged.

X-Ref Target - Figure 5-14

Figure 5-14: DNA_PORT Operation

5655540

55-Bit Unique Device Identifier (Device DNA)

Factory Programmed, Unchangeable

560

DIN DOUT

57-Bit Bit Loadable Shift Register

READ = 1

S HIFT=1

UG380_c5_14_052009

CLK

Read = 0

Table 5-51: DNA_PORT Operations

Operation DIN READ SHIFT CLK Shift Register DOUT

HOLD

X00X Hold previous value Hold previous value

READ

X1X ↑ Parallel load with 57-bit ID

Bit 56 of identifier,

which is always 1

SHIFT DIN 0 1 ↑

Shift DIN into bit 0, shift contents of Shift

Bit 56 of Shift Register

Notes:

X = Don’t care

↑ = Rising clock edge

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 169 170

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