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Spartan-6 FPGA Configuration User Guide www.xilinx.com 21
UG380 (v2.7) October 29, 2014
Design Considerations
FPGA Density Migration
The package footprint and pinouts for Spartan-6 FPGAs are designed to allow migration
between different densities within a specific family.
Likewise, an FPGA application can store other nonvolatile data in the flash memory,
requiring a larger storage device.
To support design migration between device densities, sufficient configuration memory
must be allowed to cover the largest device in the targeted package. For example, if using
the Spartan-6 XC6SLX9 device, enough configuration memory to accommodate 2.6 Mb is
required. To allow for migration to the Spartan-6 XC6SLX16 device, 3.6 Mb of
configuration memory is required.
In downloaded applications, enough space in the memory must be reserved for the largest
anticipated, uncompressed FPGA bitstream.
In self-loaded applications, a PROM footprint and the associated FPGA configuration
mode should be used to facilitate easy migration. For example, Xilinx Platform Flash
provides excellent migration between 1 to 4 Mb using the XCFxxS serial family and
between 8 to 32 Mb using the XCFxxP parallel family. If an application spans between the
two, two separate footprints should be used, one for each Platform Flash subfamily. The
XCFxxP Flash family requires a 1.8V core supply voltage input while the XCFxxS requires
3.3V. Both families provide 3.3V I/O.
The SPI serial flash vendors offer a wider migration range but do require a multi-package
footprint. For example, the Atmel DataFlash SPI serial flash family spans the range of
1to64Mb, using a single footprint that accommodates the JEDEC and EIAJ versions of the
8-pin SOIC package along with the 8-connector CASON package. The Numonyx SPI serial
flash has uses a different footprint that uses a combined 8-pin and 16-pin SOIC footprint
and is also compatible with devices from multiple SPI flash vendors.
Similarly, parallel flash supports a wide density range in a common, multi-vendor package
footprint. This overview is provided as an example; flash vendors should be consulted for
specific details.
Production Lifetime
An application’s production lifetime should be considered. Commodity memories
generally have a shorter production lifetime than the proprietary Xilinx Platform Flash
PROMs. For example, if an industrial application is built that will be manufactured for five
years or more, Xilinx Platform Flash PROMs provide better long-term availability.
Products with shorter production lifetimes can benefit from the multi-vendor pricing and
multi-sourcing of commodity memories.
Protecting the FPGA Bitstream against Unauthorized Duplication
Like processor code, the bitstream that defines the FPGA’s functionality loads into the
FPGA during power-on. Consequently, this means that an unscrupulous company can
capture the bitstream and create an unauthorized copy of the design.
Like processors, there are multiple techniques to protect the FPGA bitstream and any
intellectual property (IP) cores embedded in the FPGA. One of the most powerful
techniques is called authentication, which uses unique device “DNA,” and is described in
more detail in Chapter 5, Configuration Details. In addition, the 6SLX75/T, 6SLX100/T,
and 6SLX150/T devices also have on-chip Advanced Encryption Standard (AES)
decryption logic to provide a high degree of design security.
- Spartan-6 FPGA 1
- Configuration 1
- Revision History 3
- Table of Contents 7
- Chapter 4: User Primitives 8
- Chapter 8: Readback CRC 10
- About This Guide 13
- Additional Resources 14
- Configuration Overview 15
- Design Considerations 16
- Slave Modes 17
- UG380_c1_02_051109 18
- Serial SelectMAP 18
- MultiBoot /Safe Update 20
- Required I/O Voltages 20
- Nonvolatile Data Storage 20
- FPGA Density Migration 21
- Production Lifetime 21
- Configuration Factors 22
- Chapter 2 23
- Master Serial 26
- Slave Serial Configuration 27
- Spartan-6 28
- Microprocessor 28
- Platform Flash 32
- SelectMAP Data Loading 35
- SelectMAP Data Ordering 39
- SPI Configuration Interface 40
- SPI Flash 42
- W25Q SPI 43
- UG380_c2_14_011310 44
- Master SPI Timing Waveform 45
- Power-On Sequence Precautions 46
- SPI Serial Daisy-Chain 47
- Chapter 3 59
- Data Valid 60
- User Primitives 65
- ICAP_SPARTAN6 66
- STARTUP_SPARTAN6 67
- SUSPEND_SYNC 68
- POST_CRC_INTERNAL 69
- Chapter 4: User Primitives 70
- Configuration Details 71
- Pin Name Type 72
- Description 72
- Bitstream Overview 75
- Generating PROM Files 77
- UG380_c5_01_042909 78
- Parallel Bus Bit Order 79
- Configuration Sequence 80
- Setup (Steps 1-3) 81
- UG380_c5_04_050812 82
- Sample Mode Pins (Step 3) 83
- UG380_c5_05_042909 83
- UG380_c5_06_042909 83
- Synchronization (Step 4) 84
- Check Device ID (Step 5) 84
- UG380_c5_07_042909 84
- UG380_c5_08_042909 84
- Startup (Step 8) 86
- Phase Event 87
- Signal Name Type Access 88
- Bitstream Encryption 89
- Loading the Encryption Key 90
- Loading Encrypted Bitstreams 90
- Configuration Memory Frames 95
- Type 1 Packet 96
- Type 2 Packet 96
- Configuration Registers 97
- CRC Register 98
- CBC_REG Register 100
- IDCODE Register 100
- CSBO Register 100
- Command Register (CMD) 100
- Control Register 0 (CTL) 101
- Status Register (STAT) 102
- Configuration Packets 103
- Suspend Register (PWRDN_REG) 104
- Frame Length Register 104
- Multi-Frame Write Register 104
- HC_OPT_REG Register 105
- MODE Register 106
- CCLK_FREQ Register 107
- PU_GWE Register 107
- PU_GTS Register 107
- SEU_OPT Register 108
- DNA_PORT 109
- UG380_c5_14_052009 110
- Read = 0 110
- X = Don’t care 110
- ↑ = Rising clock edge 110
- UG380_c5_15_121112 111
- UG380_c5_16_021010 111
- UG380_c5_17_052009 112
- UG380 (v2.7) October 29, 2014 113
- Readback and Configuration 115
- Verification 115
- Readback Command Sequences 116
- AA 99 55 66 28 00 E0 0 0 117
- Verifying Readback Data 127
- UG380_c6_04_042909 128
- MSK and BIT Files 129
- Reconfiguration and MultiBoot 131
- Fallback MultiBoot 132
- IPROG Reconfiguration 134
- Watchdog Timer 135
- Readback CRC 137
- CRC Masking 138
- Chapter 8: Readback CRC 140
- Distributed RAM 141
- Post_CRC Constraints 142
- POST_CRC 143
- POST_CRC_INIT_FLAG 143
- POST_CRC_SOURCE 143
- POST_CRC_ACTION 144
- POST_CRC_FREQ 144
- Chapter 9 145
- Mixed Serial Daisy-Chains 146
- Startup Sequencing (GTS) 147
- Active DONE Driver 147
- Connect All DONE Pins 147
- DONE Pin Rise Time 147
- Bitstream Formatting 147
- Parallel Daisy-Chain 151
- Ganged SelectMAP 152
- UG380_c9_06_021710 153
- ABORT Status Word 154
- SelectMAP Reconfiguration 155
- Advanced JTAG Configurations 157
- JTAG Configuration/Readback 158
- Boundary-Scan Register 161
- Instruction Register 162
- UG380_c10_03_102014 162
- BYPASS Register 164
- JTAG Configuration Register 164
- USERCODE Register 164
- Load CFG_IN 166
- Instruction 166
- Single Device Configuration 167
- Multiple Device Configuration 168
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