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82 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
Figure 5-4 shows the power-up waveforms.
Notes relevant to Figure 5-4:
1. M0, M1 can be either 0 or 1, but must not toggle during and after the INIT rising edge.
VCCO_0
VCCO_1
VCCO_2
(4)
VCCO_5
(5)
Dual-purpose configuration pin output supply voltage.
VCCO_2 cannot be 1.2V or 1.5V during configuration.
Notes:
1. For recommended operating values, refer to DS162, Spartan-6 FPGA Data Sheet: DC and Switching
Characteristics.
2. V
BATT
or V
FS
are required only when using bitstream encryption and are only supported in Spartan-6
LX75, LX75T, LX100, LX100T, LX150, and LX150T devices.
3. V
CCAUX
must be greater than or equal to V
FS
during eFUSE programming. This requirement is not
necessary for configuration.
4. If VCCO_2 is 1.8V, V
CCAUX
must be 2.5V. If VCCO_2 is 2.5V or 3.3V, V
CCAUX
can be either 2.5V or 3.3V.
5. VCCO_5 might be needed if BPI configuration mode is used and A24 and A25 are in I/O Bank 5.
Table 5-12: Power-Up Timing
Description Symbol
Program Latency
T
PL
Power-on Reset (POR) T
POR
CCLK Output Delay T
BPIICCK
or T
SPIICCK
(2)
Program Pulse Width T
PROGRAM
Notes:
1. See Configuration Switching Characteristics in DS162, Spartan-6 FPGA Data Sheet: DC and Switching
Characteristics, for power-up timing characteristics.
2. Use T
BPIICCK
for the Master Select MAP and BPI configuration interfaces, and T
SPIICCK
for Master
Serial and SPI configuration interfaces.
X-Ref Target - Figure 5-4
Figure 5-4: Device Power-Up Timing
Table 5-11: Power Supplies Required for Configuration (Cont’d)
Pin Name
(1)
Description
UG380_c5_04_050812
V
CCINT,
V
CCO_2
, V
CCAUX
T
POR
T
PL
T
ICCK
PROGRAM_B
INIT_B
CCLK Output or Input
VALID
M0, M1
(1)
(Required)
(2)
- Spartan-6 FPGA 1
- Configuration 1
- Revision History 3
- Table of Contents 7
- Chapter 4: User Primitives 8
- Chapter 8: Readback CRC 10
- About This Guide 13
- Additional Resources 14
- Configuration Overview 15
- Design Considerations 16
- Slave Modes 17
- UG380_c1_02_051109 18
- Serial SelectMAP 18
- MultiBoot /Safe Update 20
- Required I/O Voltages 20
- Nonvolatile Data Storage 20
- FPGA Density Migration 21
- Production Lifetime 21
- Configuration Factors 22
- Chapter 2 23
- Master Serial 26
- Slave Serial Configuration 27
- Spartan-6 28
- Microprocessor 28
- Platform Flash 32
- SelectMAP Data Loading 35
- SelectMAP Data Ordering 39
- SPI Configuration Interface 40
- SPI Flash 42
- W25Q SPI 43
- UG380_c2_14_011310 44
- Master SPI Timing Waveform 45
- Power-On Sequence Precautions 46
- SPI Serial Daisy-Chain 47
- Chapter 3 59
- Data Valid 60
- User Primitives 65
- ICAP_SPARTAN6 66
- STARTUP_SPARTAN6 67
- SUSPEND_SYNC 68
- POST_CRC_INTERNAL 69
- Chapter 4: User Primitives 70
- Configuration Details 71
- Pin Name Type 72
- Description 72
- Bitstream Overview 75
- Generating PROM Files 77
- UG380_c5_01_042909 78
- Parallel Bus Bit Order 79
- Configuration Sequence 80
- Setup (Steps 1-3) 81
- UG380_c5_04_050812 82
- Sample Mode Pins (Step 3) 83
- UG380_c5_05_042909 83
- UG380_c5_06_042909 83
- Synchronization (Step 4) 84
- Check Device ID (Step 5) 84
- UG380_c5_07_042909 84
- UG380_c5_08_042909 84
- Startup (Step 8) 86
- Phase Event 87
- Signal Name Type Access 88
- Bitstream Encryption 89
- Loading the Encryption Key 90
- Loading Encrypted Bitstreams 90
- Configuration Memory Frames 95
- Type 1 Packet 96
- Type 2 Packet 96
- Configuration Registers 97
- CRC Register 98
- CBC_REG Register 100
- IDCODE Register 100
- CSBO Register 100
- Command Register (CMD) 100
- Control Register 0 (CTL) 101
- Status Register (STAT) 102
- Configuration Packets 103
- Suspend Register (PWRDN_REG) 104
- Frame Length Register 104
- Multi-Frame Write Register 104
- HC_OPT_REG Register 105
- MODE Register 106
- CCLK_FREQ Register 107
- PU_GWE Register 107
- PU_GTS Register 107
- SEU_OPT Register 108
- DNA_PORT 109
- UG380_c5_14_052009 110
- Read = 0 110
- X = Don’t care 110
- ↑ = Rising clock edge 110
- UG380_c5_15_121112 111
- UG380_c5_16_021010 111
- UG380_c5_17_052009 112
- UG380 (v2.7) October 29, 2014 113
- Readback and Configuration 115
- Verification 115
- Readback Command Sequences 116
- AA 99 55 66 28 00 E0 0 0 117
- Verifying Readback Data 127
- UG380_c6_04_042909 128
- MSK and BIT Files 129
- Reconfiguration and MultiBoot 131
- Fallback MultiBoot 132
- IPROG Reconfiguration 134
- Watchdog Timer 135
- Readback CRC 137
- CRC Masking 138
- Chapter 8: Readback CRC 140
- Distributed RAM 141
- Post_CRC Constraints 142
- POST_CRC 143
- POST_CRC_INIT_FLAG 143
- POST_CRC_SOURCE 143
- POST_CRC_ACTION 144
- POST_CRC_FREQ 144
- Chapter 9 145
- Mixed Serial Daisy-Chains 146
- Startup Sequencing (GTS) 147
- Active DONE Driver 147
- Connect All DONE Pins 147
- DONE Pin Rise Time 147
- Bitstream Formatting 147
- Parallel Daisy-Chain 151
- Ganged SelectMAP 152
- UG380_c9_06_021710 153
- ABORT Status Word 154
- SelectMAP Reconfiguration 155
- Advanced JTAG Configurations 157
- JTAG Configuration/Readback 158
- Boundary-Scan Register 161
- Instruction Register 162
- UG380_c10_03_102014 162
- BYPASS Register 164
- JTAG Configuration Register 164
- USERCODE Register 164
- Load CFG_IN 166
- Instruction 166
- Single Device Configuration 167
- Multiple Device Configuration 168
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