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16 www.xilinx.com Spartan-6 FPGA Configuration User Guide

UG380 (v2.7) October 29, 2014

Chapter 1: Configuration Overview

of UG628, Command Line Tools User Guide provides more information. After

configuration, the oscillator is turned OFF unless one of these conditions is met:

• SEU detection is used.

• CFGMCLK in STARTUP primitive is connected.

• The internal clock source is selected in SUSPEND mode (the oscillator is on only

during the WAKEUP sequence).

• Encryption is enabled.

CCLK is a dual-purpose pin. Before configuration, there is no on-chip pull-up. After

configuration, it is a user pin unless PERSIST is used.

• In Slave configuration modes, CCLK is an input.

The JTAG/boundary-scan configuration interface is always available, regardless of the

mode pin settings.

Design Considerations

To make an efficient system, it is important to consider which FPGA configuration mode

best matches the system’s requirements. Each configuration mode dedicates certain FPGA

pins and can temporarily use other pins during configuration only. These non-dedicated

pins are then released for general use when configuration is completed. See Chapter 5,

Configuration Details.

Similarly, the configuration mode can place voltage restrictions on some FPGA I/O banks.

Several different configuration options are available, and while the options are flexible,

there is often an optimal solution for each system. Several topics must be considered when

choosing the best configuration option: overall setup, speed, cost, and complexity.

FPGA Configuration Data Source

Spartan-6 FPGAs are designed for maximum flexibility. The FPGA either automatically

loads itself with configuration data from a PROM, or another external intelligent device

like a processor or microcontroller can download the configuration data to the FPGA.

Master Modes

The self-loading FPGA configuration modes, generically called Master modes, as shown in

Figure 1-1. The Master modes leverage various types of nonvolatile memories to store the

FPGA configuration information. In Master mode, the FPGA configuration bitstream

typically resides in nonvolatile memory on the same board, generally external to the

FPGA. The FPGA provides a configuration clock signal called CCLK (the source is from

either an internal oscillator or an optional external master clock source

GCLK0/USERCCLK), and the FPGA controls the configuration process.

The configuration clock frequency is user controllable in Master modes, using the BitGen

-g ConfigRate option. The default is 2 MHz.

Regardless of what option the user selects, the configuration clock in Master mode initially

starts at 1 MHz. As the FPGA clocks in the bitstream, it reads in the configuration rate

setting and then changes accordingly.

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